Section
Appendix
© Arcom Control Systems Ltd. 1987
J096 SEERAM
| Manual | PCB | Comments |
|---|---|---|
| v1 iss 2 | v1 iss 2 | 19870220 first published in this format |
J096 SEERAM
The SEERAM card is designed for use on the STEbus. It provides up to 256K Bytes of EEPROM/EPROM/RAM, or combinations thereof. The board can be jumpered to accept 8K and/or 32K devices. In the case of a mixture of 8K and 32K devices the board can keep the memory map contiguous, useful for many operating systems.
The on-board battery backup circuit means the board is ideal for use in control environments, where it is necessary to save memory contents if there is a power loss. The board also contains the circuitry necessary to program EEPROMS, including the Hitachi 58064, the AMD Am9864 and the Xicor 2864 types.
The SEERAM is very simple to use. RAM locations read/write at normal STEbus speeds. The speed at which EPROMs are read can be set by jumpers. EEPROMs are read as usual, and program cycles are simply initiated by normal STEbus write cycles. The data byte is latched in the EEPROM chip itself while the SEERAM's onboard circuitry programs the data into the main memory of the EEPROM, without further involvement by the processor.
More data cannot be written to an EEPROM until the previous data has been programmed in. This can be ensured by software wait loops, by avoiding intervals between writing to EEPROM that are shorter than the maximum programming time, or the SEERAM may interrupt the processor when the program cycle has completed.
J096 SEERAM
The circuit consists of three main parts; the STEbus interface, the memory and the EEPROM write circuitry. The STEbus interface consists of ICs 1 to 4, bus buffers, and a timing PAL IC8. Address decoding is provided by IC12, which can be jumpered so that memory starts on any 64K-byte boundary. Chip select decoding is provided by the logic arrays IC11 and IC14. The chip selects are taken to the memory ICs via opto-isolators, which are only active when the supply voltage is greater than 4.65 V. This technique enables the RAM chips to be battery backed up, and protects against power on/off glitches.
Logic array IC6 provides the necessary strobes for programming EEPROMs. Although the programming requirements for EEPROMs vary between manufacturers, this manual restricts its attention to those three indicated above. For other types refer to the manufacturer's data sheets.
J096 SEERAM
J096 SEERAM
To use the SEERAM is fairly straightforward, mainly just a matter of setting up the links correctly. First set up Link 7 to indicate the base address of the board and the number of 32K chips required. Fill Link 8 to indicate that all the IC sockets are in use. Then fill Link 9 if any of the devices are EEPROMs. Make links 3-6 as required for speed of the devices. Finally configure the groups of links near the memory ICs for the correct device type. The board is now ready to use.
There are several very easy ways of using EEPROMs on the SEERAM. An EEPROM program cycle is initiated by a normal STEbus write cycle. The data byte is latched in the EEPROM chip itself and held while the SEERAM's onboard circuitry programs the data into the main memory of the EEPROH. More data cannot be written to an EEPROM until the previous data has been programmed in. There are several ways in which this can be ensured.
Waiting in a software loop for longer than the maximum programming time.
Polling data bit 7 until the EEPROM indicates program-cycle-finished by no longer inverting the data bit 7 currently being programmed. This method can only be used on certain types of EEPROMs, so the manufacturer's data sheet should be consulted.
Jumpering the SEERAM to interrupt the processor on the end of an EEPROM program cycle. The interrupt handler may initiate the next program cycle if needed, and negate the ATNRQ* line by reading the SEERAM.
The ATNRQ* may be asserted by the READY/!BUSY signal (only found on pin 1 of AMD type EEPROMs) goes high (link LK3 made), or when the program pulse goes inactive (link LK3 not made). LK1 must be jumpered to select which ATNRQ* line is used (if used).
If the software can guarantee to write data to EEPROM less frequently than the maximum programming time, then no overwriting protection is needed.
Method 1 is the simplest, and allows the programmer to decide whether to have the software wait to write more data or return to some more productive task.
One point worth noting is that if you are using EEPROMs, especially older types, is that before programming a byte you may need to erase the byte by writing $FF to the location. During an EEPROM write cycle visual indication is provided by the red LED at the front of the board, this is useful since it is not possible to program an EEPROM more than 10,000 times, and inadvertently treating the EEPROM as a RAM chip could soon damage it, thus the LED acts as a warning against this happening.
J096 SEERAM
J096 SEERAM
J096 SEERAM
J096 SEERAM
